An Si570 Alternative for SoftRock Style Receivers

The crystal controlled SoftRock receivers developed by Tony Parks (KB9YIG) are responsible for introducing a significant number of people to Software Defined Radio (SDR).  And for those who don’t want to be stuck on a single frequency there are the SoftRock Ensemble receivers that use the Silicon Laboratories’ Si570 Programmable Crystal Oscillator (XO) for frequency control.  In fact, frequency synthesizers using the Si570 have become the de-factor standard for these type of receivers.

The only problem with this is the Si570 itself.  They can be difficult to find in small quantities and a little expensive when you can find them (SDR-Kits does have them available in packs of 10 if you so desire). Therefore, when I started working on my own receiver I decided to look around for alternatives.

It wasn’t long before I ran across the Cypress CY22150.  This is a general purpose 3.3V clock generator.  With an external reference it will produce frequencies from 80 kHz to 166.6 MHz and can be programmed in the field through an I2C interface.  Since they are available in single quantities from Digikey for less than $3.00 USD, I decided to buy a few and try them out.

Using the CY22150

The test circuit is shown below.  X1 is a canned external oscillator that provides the reference frequency (I used a 50 MHz oscillator for the test circuit).  U1 is the CY22150 itself.  The clock output is taken from pin 14.  The resistors shown are not part of the clock circuit per-se, but the terminating resistors for the I2C bus.

CY22150_Schematic

Using the CY22150 consists primarily of putting the proper values into the registers.  There are a number of support registers that need to be set but the most important are those that determine the output frequency; P, Q, and the Divider.

The clock output frequency can be calculated as:

cy22150_equ_1

where

cy22150_eqn_2

There are various combinations of P, Q, and the Divider that will give a specific frequency and it might seem like you can choose any of them that will work. However, there are some guidelines for best performance.

  • fref / Q should not go below 250 kHz for stable operation.
  • fref * P / Q should be between 100 MHz and 400 MHz for stable operation.
  • use the minimum Q and maximum P consistent with the above for best phase noise.

Based on these guidelines, a good algorithm for P, Q, and Divider value is:

  1. Calculate the allowed range of Q.
  2. Calculate the allowed range of the Divider.
  3. For each combination of Q and the Divider calculate the value of P that will get you closest to the desired output frequency.
  4. Use the value of Q, P, and the Divider that gets you closest to the desired frequency.

Sample code to implement this algorithm is given below.

double f_ref = F_REF;
double f_out = F_OUT;
double q_min = 2;
double q_max = (int)(f_ref / 250000.0);
double d_min = (int)(1.0 + 100000000.0 / f_out);
double d_max = (int)(1.0 + 400000000.0 / f_out) - 1.0;
double f_test, f_diff;
double f_track = f_out;
double p_test, q_test, d_test;
int p, q, d;

for (q_test = q_min; q_test <= q_max; q_test++)
{
   for (d_test = d_max; d_test >= d_min; d_test--)
   {
      p_test = (f_out / f_ref) * q_test * d_test;
      p_test = ((p_test - (int)p_test) > .5) ?  (int)(p_test + 1.0) : (int)p_test;
      f_test = (f_ref * p_test) / (q_test * d_test);
      f_diff = ((f_test - f_out) > 0.0) ? (f_test - f_out) : (f_out - f_test);
      if (f_diff < f_track)
      {
         f_track = f_diff;
         p = (int)p_test;
         q = (int)q_test;
         d = (int)d_test;
      }
   }
}

Appropriate values for the remaining registers can be obtained from the datasheet and written along with the P, Q, and Divider values to the CY22150 via the I2C bus. To test it all I put together an extio dll to control the clock circuit from HDSDR and used it as the oscillator for an SDR I’m putting together.  It worked well and was stable enough to allow WSPR reception so I think I’ll be using this circuit in more of my projects.

Something to keep in mind. If you take a look at the equation used to calculate the clock generator’s output frequency you’ll realize you’re not going to get the frequency resolution from this circuit you might get from others. But that’s one of the advantages of working with SDR. You don’t have to be exact with your local oscillator, you just have to get close enough to put your frequency of interest within the processing bandwidth, and in most cases this circuit will work just fine.

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